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confidential rev. 1.1 11/07 copyright? 2007 by silicon laboratories si4702-b16 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. silicon laboratories confidential. information contained herein is covered under non-disclosure agreement (nda). si4702-b16 b roadcast fm r adio t uner for p ortable a pplications features applications description the si4702 integrates the complete tuner function from antenna input to stereo audio output for fm broadcast radio reception. functional block diagram ? this data sheet applies to si4702 firmware 16 ? worldwide fm band support (76?108 mhz) ? digital low-if receiver ? frequency synthesizer with integrated vco ? seek tuning ? automatic frequency control (afc) ? automatic gain control (agc) ? excellent overload immunity ? signal strength measurement ? programmable de-emphasis (50/75 s) ? adaptive noise suppression ? volume control ? line-level analog output ? 32.768 khz reference clock ? 2-wire and 3-wire control interface ? 2.7 to 5.5 v supply voltage ? integrated ldo regulator allows direct connection to battery ? 3 x 3 mm 20-pin qfn package z pb-free/rohs compliant ? integrated crystal oscillator ? cellular handsets ? mp3 players ? portable radios ? usb fm radio ? pdas ? notebook pcs ? portable navigation ? consumer electronics vio controller i adc q adc si4702 dsp filter demod mpx audio sclk sdio control interface sen dac dac rout lout 0 / 90 low-if rssi tune gpio amplifier gpio rst rfgnd lna fmip afc agc pga rclk reg va vd 32.768 khz 2.7?5.5 v headphone cable xtal osc patents pending notes: 1. to ensure proper operation and fm receiver performance, follow the guidelines in ?an231: si4700/ 01/02/03 headphone and antenna interface.? silicon laboratories will evaluate schematics and layouts for qualified customers. 2. place si4702 as close as possible to the antenna jack, and keep the fmip trace as short as possible. ordering information: see page 35. pin assignments (top view) si4702-gm gnd pad 1 gpio1 rclk gnd lout rout rst nc gnd sdio sclk gnd fmip rfgnd gpio2 v d nc gpio3 v io sen v a 2 5 4 3 6 15 12 13 14 7 10 9 8 11 17 18 19 20 16
si4702-b16 2 confidential rev. 1.1
si4702-b16 confidential rev. 1.1 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.2. fm receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3. general purpose i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4. stereo audio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5. tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6. reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.7. control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8. reset, powerup, and powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.9. audio output summation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.10. initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.11. programming guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5. register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6. register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 7. pin descriptions: si4702-gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9. package markings (top marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1. si4702 top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2. top mark explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10. package outline: si4702-gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11. pcb land pattern: si4702- gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12. additional reference resour ces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
si4702-b16 4 confidential rev. 1.1 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit digital supply voltage v d 2.7 ? 5.5 v analog supply voltage v a 2.7 ? 5.5 v interface supply voltage v io 1.5 ? 3.6 v digital power supply power-up rise time v drise 10 ? ? s analog power su pply power-up rise time v arise 10 ? ? s interface power supply power-up rise time v iorise 10 ? ? s ambient temperature t a ?20 25 85 c note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at v d = v a = 3.3 v and 25 c unless otherwise stated. pa rameters are tested in production unless otherwise stated. table 2. absolute maximum ratings 1,2 parameter symbol value unit digital supply voltage v d ?0.5 to 5.8 v analog supply voltage v a ?0.5 to 5.8 v interface supply voltage v io ?0.5 to 3.9 v input current 3 i in 10 ma input voltage 3 v in ?0.3 to (v io + 0.3) v operating temperature t op ?40 to 95 c storage temperature t stg ?55 to 150 c rf input level 4 0.4 v pk notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data shee t. exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. the si4702 device is a high-performance rf integrated circuit with an esd rating of < 2 kv hbm. handling and assembly of this device should only be done at esd-protected workstations. 3. for input pins sclk, sen , sdio, rst , rclk, gpio1, gpio2, and gpio3. 4. at rf input pins.
si4702-b16 confidential rev. 1.1 5 table 3. dc characteristics (v d =v a = 2.7 to 3.6 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit analog operating supply current 1 i a enable = 1 ? 13.2 ? ma digital operating supply current 1 i d enable = 1 ? 4.2 ? ma interface operating supply current 1 i io enable = 1 ? 0.4 ? ma total operating supply current 1,2,3,4 i op enable = 1, low snr signal ? 18.8 24.5 ma total operating supply current 1,2,3 i op enable = 1 ? 17.8 23.6 ma analog powerdown supply current 1,6 i apd enable = 0 ? 1.9 ? ua digital powerdown supply current 1,6 i dpd enable = 0 ? 1.9 ? ua interface powerdown supply current 1,6,7 i iopd enable = 0 sclk, rclk inactive ?2.0?ua total powerdown supply current 1,6 i pd enable = 0 ? 5.8 14.1 ua high level input voltage 8 v ih 0.7 x v io ?v io +0.3 v low level input voltage 8 v il ?0.3 ? 0.3 x v io v high level input current 8 i ih v in =v io =3.6v ?10 ? 10 a low level input current 8 i il v in =0v, v io =3.6v ?10 ? 10 a high level output voltage 9 v oh i out = 500 a 0.8 x v io ??v low level output voltage 9 v ol i out =?500a ? ? 0.2xv io v notes: 1. refer to register 02h, "power configuration" on page 22 for enable bit description. 2. the lna is automatically switched to higher current mode for optimum sensitivity in low snr conditions. 3. analog and digital supply currents are simultaneously adjusted based on snr level. 4. stereo and rds functionality are disabled at low snr levels. 5. rds functionality only available for si4703. 6. refer to section 4.8. "reset, powerup, and powerdown" on page 17. 7. all gpio pins are grounded. 8. for input pins sclk, sen , sdio, rst , rclk, gpio1, gpio2, and gpio3. 9. for output pins sdio, gpio1, gpio2, and gpio3.
si4702-b16 6 confidential rev. 1.1 figure 1. reset timing parameters for busmode select method 1 (gpio3 = 0) table 4. reset timing characteristics (busmode select method 1) 1,2,3 parameter symbol test condition min typ max unit rst pulse width and gpio3 setup to rst t gsrst1 4 gpio3 = 0 100 ? ? s sen and sdio setup to rst t srst1 30 ? ? ns sen , sdio, and gpio3 hold from rst t hrst1 30 ? ? ns notes: 1. when selecting 2-wire mode, the user must ensure that a 2- wire start condition (falling edge of sdio while sclk is high) does not occur within 300 ns before the rising edge of rst . 2. when selecting 3-wire mode, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . 3. when selecting 2-wire mode, the user must ensure th at sclk is high during the rising edge of rst and that it stays high until after the first start condition. 4. if gpio3 is driven low by the user, minimum t gsrst1 is only 30 ns. if gpio3 is hi-z, minimum t gsrst1 is 100 s to provide time for an on-chip 1 m pulldown device (active while rst is low) to discharge the pin. 70% 30% sen, sdio 70% 30% gpio3 70% 30% t gsrst1 rst t hrst1 t srst1
si4702-b16 confidential rev. 1.1 7 figure 2. reset timing parameters for busmode select method 2 (gpio3 = 1) table 5. reset timing characteristics (busmode select method 2) 1,2,3 parameter symbol test co ndition min typ max unit gpio1 and gpio3 setup to rst t srst2 gpio3 = 1 30 ? ? ns gpio1 and gpio3 hold from rst t hrst2 30 ? ? ns notes: 1. when selecting 2-wire mode, the user must ensure that a 2- wire start condition (falling edge of sdio while sclk is high) does not occur within 300 ns before the rising edge of rst . 2. when selecting 3-wire mode, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . 3. when selecting 2-wire mode, the user must ensure that sclk is high during the rising edge of rst and stays high until after the first start condition. 70% 30% t srst2 rst t hrst2 gpio3 70% 30% gpio1 70% 30%
si4702-b16 8 confidential rev. 1.1 figure 3. 3-wire control interface write timing parameters figure 4. 3-wire control interface read timing parameters table 6. 3-wire control interface characteristics (v d =v a = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk frequency f clk 0?2.5mhz sclk high time t high 25 ? ? ns sclk low time t low 25 ? ? ns sdio input, sen to sclk setup t s 20 ? ? ns sdio input to sclk hold t hsdio 10 ? ? ns sen input to sclk hold t hsen1 10 ? ? ns sen input to sclk hold t hsen2 10 ? ? ns sclk to sdio output valid t cdv read 2 ? 25 ns sclk to sdio output high z t cdz read 2 ? 25 ns note: when selecting 3-wire mode, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . sclk 70% 30% sen 70% 30% sdio a7 a0 70% 30% t s t s t hsdio t hsen1 a6-a5, r/w, a4-a1 address in data in d15 d14-d1 d0 t high t low t hsen2 ? cycle bus turnaround sclk 70% 30% sen 70% 30% sdio 80% 20% t hsdio t cdv t cdz address in data out a7 a0 a6-a5, r/w, a4-a1 d15 d14-d1 d0 t s t s t hsen1 t hsen2
si4702-b16 confidential rev. 1.1 9 table 7. 2-wire control interface characteristics 1,2,3 (v d =v a = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test co ndition min typ max unit sclk frequency f scl 0?400khz sclk low time t low 1.3 ? ? s sclk high time t high 0.6 ? ? s sclk input to sdio setup (start) t su:sta 0.6 ? ? s sclk input to sdio hold (start) t hd:sta 0.6 ? ? s sdio input to sclk setup t su:dat 100 ? ? ns sdio input to sclk hold 4, 5 t hd:dat 0?900ns sclk input to sdio setup (stop) t su:sto 0.6 ? ? s stop to start time t buf 1.3 ? ? s sdio output fall time t f:out 20 + 0.1 c b ?250ns sdio input, sclk rise/fall time t f:in t r:in 20 + 0.1 c b ?300ns sclk, sdio capacitive loading c b ??50pf input filter pu lse suppression t sp ? ? 50 ns notes: 1. when v io = 0 v, sclk and sdio are low-impedance. 2. when selecting 2-wire mode, the user must ensure th at sclk is high during the rising edge of rst and that it stays high until after the first start condition. 3. when selecting 2-wire mode, the user must ensure that a 2- wire start condition (falling edge of sdio while sclk is high) does not occur within 300 ns before the rising edge of rst . 4. as a transmitter, the si4703 delays sdio by a minimum of 300 ns from the v ih threshold of sclk to comply with the 0ns t hd:dat specification. 5. the maximum t hd:dat has only to be met when f scl = 400 khz. at frequencies below 400 khz, t hd:dat may be violated so long as all other timing parameters are met.
si4702-b16 10 confidential rev. 1.1 figure 5. 2-wire control interface read and write timing parameters figure 6. 2-wire control interface read and write timing diagram sclk 70% 30% sdio 70% 30% start start stop t f:in t r:in t low t high t hd:sta t su:sta t su:sto t sp t buf t su:dat t r:in t hd:dat t f:in, t f:out sclk sdio start stop address + r/w ack data ack data ack a6-a0, r/w d7-d0 d7-d0
si4702-b16 confidential rev. 1.1 11 table 8. fm receiver characteristics 1,2 (v d =v a = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit input frequency f rf 76 ? 108 mhz sensitivity 3,4,5,6,7,8 (s+n)/n = 26 db ? 2.2 3.5 vemf sensitivity (50 matching network) 3,4,5,6 (s+n)/n = 26 db ? 1.1 ? vemf lna input resistance 8,9 345k lna input capacitance 8,9 456pf input ip3 8,10 104 108 ? dbvemf am suppression 3,4,5,8,9 m=0.3 40 55 ? db adjacent channel selectivity 200 khz 35 50 ? db alternate channel selectivity 400 khz 60 70 ? db spurious response rejection 8 in-band 35 ? ? db rclk frequency ? 32.768 ? khz rclk frequency tolerance 11 space[1:0] = 00 or 01 ?200 ? 200 ppm space[1:0] = 10 ?50 ? 50 audio output voltage 3,4,5,9 72 80 90 mv rms audio output l/r imbalance 3,4,9,12 ?? 1 db audio band limits 3,4,8,9 1.5 db 30 ? 15 k hz audio stereo separation 3,9,12 25 ? ? db mono/stereo switching level 3,8,12 blndadj = 10 10 db stereo separation ? 34 ? dbvemf notes: 1. additional testing information is available in application note an 234. volume = maximum for all tests. 2. to ensure proper operation and fm receiver performa nce, follow the guidelines in ?an231: si4700/01/02/03 headphone and antenna interface.? silicon laboratori es will evaluate schematics and layouts for qualified customers. 3. f mod = 1 khz, 75 s de-emphasis. 4. mono = 1, and l = r unless noted otherwise. 5. f = 22.5 khz. 6. b af = 300 hz to 15 khz, a-weighted. 7. typical sensitivity with headphone matching network. 8. guaranteed by characterization. 9. measured at v emf =1mv, f rf = 76 to 108 mhz. 10. |f 2 ? f 1 | > 1 mhz, f 0 =2xf 1 ? f 2 . agc is disabled by setting agcd = 1. refer to section "6. register descriptions" on page 21. 11. the channel spacing is selected with the space[1:0] bits. refer to section ?6. register descriptions?. seek/tune timing is guaranteed for 100 and 200 khz channel spacing. 12. f = 75 khz. 13. the de-emphasis time constant is selected with the de bit. refer to section ?6. register descriptions?. 14. at lout and rout pins. 15. do not enable stc interrupts before the powerup time is complete. if stc interrupts are enabled before the powerup time is complete, an interrupt will be generated within the powerup interval when the initial default tune operation is complete. see "an230: si4700/01/02/03 programmer?s guide" for more information. 16. min and max at room temperature (25 c).
si4702-b16 12 confidential rev. 1.1 audio mono s/n 3,4,5,6,9 55 59 ? db audio stereo s/n 5,8 blndadj = 10 ? 58 ? db audio thd 3,4,9,12 ?0.10.5 % de-emphasis time constant 13 de = 0 70 75 80 s de = 1 45 50 54 s audio common mode voltage 14 enable = 1 0.7 0.8 0.9 v audio common mode voltage 14 enable = 0 ahizen = 1 ?0.5xv io ?v audio output load resistance 8,14 r l single-ended 10 ? ? k audio output load capacitance 8,14 c l single-ended ? ? 50 pf seek/tune time 8,11 space[1:0] = 0x, rclk tolerance=200ppm, (x = 0 or 1) ??60ms/ channel powerup time 15 from powerdown (write enable bit to 1) ??110ms rssi offset 16 input levels of 8 and 60 dbv at rf input ?3 ? 3 db table 8. fm receiver characteristics 1,2 (continued) (v d =v a = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit notes: 1. additional testing information is available in application note an 234. volume = maximum for all tests. 2. to ensure proper operation and fm receiver performa nce, follow the guidelines in ?an231: si4700/01/02/03 headphone and antenna interface.? silicon laboratori es will evaluate schematics and layouts for qualified customers. 3. f mod = 1 khz, 75 s de-emphasis. 4. mono = 1, and l = r unless noted otherwise. 5. f = 22.5 khz. 6. b af = 300 hz to 15 khz, a-weighted. 7. typical sensitivity with headphone matching network. 8. guaranteed by characterization. 9. measured at v emf =1mv, f rf = 76 to 108 mhz. 10. |f 2 ? f 1 | > 1 mhz, f 0 =2xf 1 ? f 2 . agc is disabled by setting agcd = 1. refer to section "6. register descriptions" on page 21. 11. the channel spacing is selected with the space[1:0] bits. refer to section ?6. register descriptions?. seek/tune timing is guaranteed for 100 and 200 khz channel spacing. 12. f = 75 khz. 13. the de-emphasis time constant is selected with the de bit. refer to section ?6. register descriptions?. 14. at lout and rout pins. 15. do not enable stc interrupts before the powerup time is complete. if stc interrupts are enabled before the powerup time is complete, an interrupt will be generated within the powerup interval when the initial default tune operation is complete. see "an230: si4700/01/02/03 programmer?s guide" for more information. 16. min and max at room temperature (25 c).
si4702-b16 confidential rev. 1.1 13 2. typical application schematic notes: 1. place c1 close to v d pin. 2. all grounds connect directly to gnd plane on pcb. 3. pins 1 and 20 are no connects; leave floating. 4. fm receiver performance is subject to adherence to antenna design guidelines in ?an231: si4700/01/02/03 headphone and antenna interface.? failure to use these guidelines will negatively affect the performance of the si4702, particularly in weak-signal and noisy envi ronments. silicon laboratories will evaluate schematics and layouts for qualified customers. 5. pin 2 connects to the antenna interface, refer to ?an231: si4700/01/02/03 headphone and antenna interface.? 6. place si4702 as close as possible to the antenna ja ck, and keep the fmip trace as short as possible. 7. refer to si4702 internal crystal oscillator errata. 8. refer to "an299: external 32.768 khz crystal oscillator." 3. bill of materials component(s) value/description supplier(s) c1 supply bypass capacitor, 22 nf, 20%, z5u/x7r murata u1 si4702 fm radio t uner silicon laboratories c2, c3 crystal load capacitors, 22 pf, 5%, cog (optional for cryst al oscillator option) venkel x1 32.768 khz crystal (optional fo r crystal oscillator option) epson 20 19 18 17 16 nc fmip rfgnd gnd rst gnd lout rout gnd vd nc gpio1 gpio2 gpio3 va sen sclk sdio rclk vio sen sclk sdio 1 2 3 4 5 15 14 13 12 11 6 7 8 9 10 rst rclk c1 gnd pad lout rout vbattery 2.7 to 5.5 v gpio1 gpio2 gpio3 vio 1.5 to 3.6 v fmip rfgnd c2 c3 x1 rclk gpio3 optional: for crystal oscillator option
si4702-b16 14 confidential rev. 1.1 4. functional description figure 7. si4702 fm receiver block diagram 4.1. overview the si4702 extends silic on laboratorie s? si4700 fm tuner family and further increases the ease and attractiveness of adding fm radio reception to mobile devices through small size and board area, minimum component count, flexib le programmability, and superior, proven performance. si4702 software is backwards-compatible to existing si4700 fm tuner designs and leverages silicon laboratories' highly-successful and patented si4700 fm tuner. the si4702 benefits from proven digital integration and 100% cmos process technology, resulting in a completely integrated soluti on. it is the industry's smallest footprint fm tuner ic requiring only 10 mm 2 of board space and one external bypass capacitor. the device offers significant programmability and caters to the subjective nature of fm listeners and variable fm broadcast environments world-wide through a simplified programming interface and mature functionality. the si4702 is based on the superior, proven performance of silicon laboratories' si4700 architecture offering unmatched interference rejection and leading sensitivity. the device uses the same programming interface as the si4700 and supports multiple bus modes. powe r management is also simplified with an integrated regulator allowing direct connection to a 2.7 to 5.5 v battery. the si4702 device?s high level of integration and complete fm system prod uction testing increases quality to manufacturers, improves device yields, and simplifies device manufact uring and final testing. the si4703, a pin-compatible device that supports rds/rbds, is also available. the si4703 incorporates a digital processor for the european radio data system (rds) and the u.s. radio broadcast data system (rbds) including all required symbol decoding, block synchronization, error detection, and error correction functions. 4.2. fm receiver the si4702?s patented, digital, low-if architecture reduces the number of external components and eliminates the need for factory adjustments. the receive (rx) section integrates a low-noise amplifier (lna) supporting the worldwide fm broadcast band (76 to 108 mhz). an automatic gain control (agc) circuit controls the gain of the lna to optimize sensitivity and rejection of strong interferers. for testing purposes, the agc can be disabled with the agcd bit. refer to section 6. "register descriptions" on page 21 for additional programming and configuration information. the si4702 architecture and antenna design increases system performance. to ensure proper performance and operation, designers should refer to the guidelines in "an231: si4700/01/02/03 headphone and antenna interface". conformance to these guidelines will help ensure excellent performance even in weak-signal or noisy environments. vio controller i adc q adc si4702 dsp filter demod mpx audio sclk sdio control interface sen dac dac rout lout 0 / 90 low-if rssi tune gpio amplifier gpio rst rfgnd lna fmip afc agc pga rclk reg va vd 32.768 khz 2.7 - 5.5 v headphone cable xtal osc
si4702-b16 confidential rev. 1.1 15 an image-reject mixer downconverts the rf signal to low-if. the quadrature mixer output is amplified, filtered, and digitized with high-resolution analog-to-digital converters (adcs). this advanced architecture achieves superior performance by using digital signal processing (dsp) to perform channel selection, fm demodulation, and stereo audio processing compared to traditional analog architectures. 4.3. general purpose i/o pins pins gpio1?3 can serve multiple functions. gpio1 and gpio3 can be used to select between 2-wire and 3-wire modes for the control interface as the device is brought out of reset. see section ?4.8. reset, powerup, and powerdown?. after powerup of the device, pins gpio1?3 can be used as general-purpose inputs/ outputs, and pins gpio2?3 can be used as interrupt request pins for seek/tune and as a stereo/mono indicator. see register 04h, bits [5:0], in section 6. "register descriptions" on page 21 for information on controlling these pins. it is recommended that the gpio2?3 pins not be used as interrupt request outputs until the powerup time has completed (see section ?4.8. reset, powerup, and powerdown?). the gpio3 pin has an internal, 1 m , 15% pull-down resistor that is only active while rst is low. general-purpose input/output functionality is available regardless of the state of the v a and v d supplies, or the enable and disable bits. 4.4. stereo audio processing the output of the fm demodulator is a stereo multiplexed (mpx) signal. the mpx standard was developed in 1961 and is used worldwide. today's mpx signal format consists of left +right (l+r) audio, left?right (l?r) audio, a 19 khz pilot tone, and rds/rbds data as shown in figure 8. figure 8. mpx signal spectrum the si4702's integrated stereo decoder automatically decodes the mpx signal. the 0 to 15 khz (l+r) signal is the mono output of the fm tuner. stereo is generated from the (l+r), (l-r), and a 19 khz pilot tone. the pilot tone is used as a reference to recover the (l-r) signal. separate left and right channels are obtained by adding and subtracting the (l+r) and (l-r) signals, respectively. adaptive noise suppression is employed to gradually combine the stereo left and right audio channels to a mono (l+r) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. the signal level range over which the stereo to mono blending occurs can be adjusted by setting the blndadj[1:0] register. stereo/mono status can be monitored with the st register bit and mono operation can be forced wi th the mono register bit. pre-emphasis and de-emphasis is a technique used by fm broadcasters to improve the signal-to-noise ratio of fm receivers by reducing the effects of high frequency interference and noise. when the fm signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. all fm receivers incorporate a de-emphasis filter which attenuates high frequencies to restore a flat frequency response. two time constants, 50 or 75 s, are used in various regions. the de-emphasis time constant is programmable with the de bit. high-fidelity stereo digital-to-analog converters (dacs) drive analog audio signals onto the lout and rout pins. the audio output may be muted with the dmute bit. volume can be adjusted digitally with the volume[3:0] bits. the volume dynamic range can be set to either ?28 dbfs (default) or ?58 dbfs by setting volext=1. the soft mute feature is available to attenuate the audio outputs and minimize audible noise in weak-signal conditions. the soft mute attack and decay rate can be adjusted with the smuter[1:0] bits where 00 is the fastest setting. the soft mute attenuation level can be adjusted with the smutea[1:0] bits where 00 is the most attenuated. the soft mute disable (dsmute) bit may be set high to disable this feature. 4.5. tuning the si4702 uses silicon la boratories? patented and proven frequency synthesizer technology including a completely integrated vco. the frequency synthesizer generates the q uadrature local oscilla tor signal used to downconvert the rf input to a low intermediate frequency. the vco freque ncy is locked to the reference clock and adjusted with an automatic frequency control (afc) servo loop during reception. the tuning frequency is defined as: 057 53 38 23 19 15 frequency (khz) modulation level stereo audio left - right rds/ rbds mono audio left + right stereo pilot freq (mhz) spacing (khz) channel bottom of band (mhz) + =
si4702-b16 16 confidential rev. 1.1 channel spacing of 50, 100 or 200 khz is selected with bits space[1:0]. the channel is selected with bits chan[9:0]. band selection for japan, japan wideband, or europe/u.s./asia is set with band[1:0]. the tuning operation begins by setting the tune bit. after tuning completes, the seek/tune co mplete (stc) bit will be set and the rssi level is available by reading bits rssi[7:0]. the tune bit must be set low after the stc bit is set high in order to complete the tune operation and clear the stc bit. seek tuning searches up or down for a channel with an rssi greater than or equal to the seek threshold set with the seekth[7:0] bits. in addition, optional snr and/or impulse noise detector criteria may be used to qualify valid stations. th e sksnr[3:0] bits set the required snr threshold. th e skcnt[3:0] bits set the impulse noise threshold. us ing the extra seek qualifiers can reduce false stops and, in combination with lowering the rssi seek threshold, increase the number of found stations. the snr and impulse noise detectors are disabled by default for backwards-compatibility. two seek modes are available. when the seek mode (skmode) bit is low and a se ek is initiated, the device seeks through the band, wraps from one band edge to the other, and continues seek ing. if the seek operation is unable to find a valid channel, the seek failure/band limit (sf/bl) bit is set high and the device returns to the channel selected before the seek operation began. when the skmode bit is high and a seek is initiated, the device seeks through the band until the band limit is reached and the sf/bl bit is set high. a seek operation is initiated by setting the seek and seekup bits. after the seek operation completes, the stc bit is set, and the rssi level and tuned channel are available by reading bits rssi[7:0] and bits readchan[9:0]. during a seek operation, readchan[9:0] is also updated and may be read to determine and report seek progress. the stc bit is set after the seek operation completes. the channel is valid if the seek operation completes and the sf/bl bit is set low. at other times, such as before a seek operation or after a seek completes and the sf/bl bit is set high, the channe l is valid if the afc rail (afcrl) bit is set low and the value of rssi[7:0] is greater than or equal to seekth[7:0]. note that if a valid channel is found but the afcrl bit is set, the audio output is muted as in the softmute case discussed in section ?4.4. stereo au dio processing?. the seek bit must be set low after the stc bit is set high in order to complete the seek operation. setting the stc bit low clears stc status and sf/bl bits. the seek operation may be aborted by setting the seek bit low at any time. the device can be configured to generate an interrupt on gpio2 when a tune or seek operation completes. setting the seek/tune complete (stcien) bit and gpio2[1:0] = 01 will configure gpio2 for a 5 ms low interrupt when the stc bit is set by the device. for additional recommendations on optimizing the seek function, consult "an284 : si4700/01/02/03 seek adjustability and settings." 4.6. reference clock the si4702 accepts a 32.768 khz reference clock to the rclk pin. the reference clock is required whenever the enable bit is set high. refer to table 3, ?dc characteristics,? on page 5 for input switching voltage levels and table 8, "fm rece iver characteristics," on page 11 for frequency tolerance information. an onboard crystal oscillator is available to generate the 32.768 khz reference when an external crystal and load capacitors are provided. refer to 2. "typical application schematic" on page 13. the os cillator must be enabled or disabled while in powerdown (enable = 0) as shown in figure 9 on page 19. register 07h, bits [13:0], must be preserved as 0x0100 while in powerdown. note that the rclk voltage levels are not specified. when the crystal oscillator is used, the typical rclk voltage level is 0.3 v pk-pk . 4.6.1. si4702 internal crystal oscillator errata the si4702-b16 seek/tune performance may be affected by data activity on the sdio bus when using the integrated internal oscillator. sd io activity results from polling the tuner for st atus or communicating with other devices that share the sdio bus. if there is sdio bus activity while the si4702-b16 is performing the seek/tune function, the cryst al oscillator may experience jitter, which may result in mistunes and/or false stops. sdio activity during all ot her operational states does not affect performance. for best seek/tun e results, silicon laboratories recommends that all sdio data traffic be suspended during si4702-b16 seek and tune operations. this is achieved by keeping the bus quiet for all other devices on the bus and delaying tu ner polling until the tune or seek operation is complete. the stc (seek/tune complete) interrupt should be used instea d of polling to determine when a seek/tune operation is complete. refer to the si4702-b16 data sheet for specified seek/ tune times and register use guidelines. the layout guidelines in si4700/01/02/03 evaluation board user?s guide, section 8.3. "si4702 daughter card", should be followed to help ensure robust fm performance. refer to the posted si4702 internal crystal oscillator errata for more information.
si4702-b16 confidential rev. 1.1 17 4.7. control interface two-wire, slave-transceiver, and three-wire interfaces are provided for the controller ic to read and write the control registers. refer to ?4.8. reset, powerup, and powerdown? for a description of bus mode selection. registers may be written and read when the v io supply is applied regardless of the state of the v d or v a supplies. rclk is not required for proper register operation. 4.7.1. 3-wire control interface for three-wire operation, a transfer begins when the sen pin is sampled low by the device on a rising sclk edge. the control word is la tched internally on rising sclk edges and is nine bits in length, comprised of a four-bit chip address, a7:a4 = 0110b, a read/write bit (write = 0 and read = 1), and a four-bit register address, a3:a0. the ordering of the control word is a7:a5, r/w , a4:a0. refer to section 5. "register summary" on page 20 for a list of all regi sters and their addresses. for write operations, the seri al control word is followed by a 16-bit data word and is latched internally on rising sclk edges. for read operations, a bus tu rnaround of half a cycle is followed by a 16-bit data word shifted out on rising sclk edges and is clocked into the system controller on falling sclk edges. the transfer ends on the rising sclk edge after sen is set high. note that 26 sclk cycles are required for a transfer; however, sclk may run continuously. for details on timing specifications and diagrams, refer to table 6, ?3-wire control in terface characteristics,? on page 8, figure 3, ?3-wire control interface write timing parameters,? on page 8, and figure 4, ?3-wire control interface read timing parameters,? on page 8. 4.7.2. 2-wire control interface for two-wire operation, the sclk and sdio pins function in open-drain mode (pull-down only) and must be pulled up by an external device. a transfer begins with the start condition (falling edge of sdio while sclk is high). the control wo rd is latched internally on rising sclk edges and is eight bits in length, comprised of a seven-bit device address equal to 0010000b, and a read/write bit (write = 0 and read = 1). the device acknowledges the address by driving sdio low after the next falling sclk edge, for one cycle. for write operations, the device acknowledge is followed by an eight bit data word latched internally on rising edges of sclk. the device acknowledges each byte of data written by driving sdio lo w after the next falling sclk edge, for one cycle. an internal address counter automatically increments to allow continuous data byte writes, starting with the upper byte of register 02h, followed by the lower byte of register 02h, and onward until the lower byte of the last register is reached. the internal address counter then automatically wraps around to the upper byte of register 00h and proceeds from there until continuous writes end. data transfer ends with the stop condition (rising edge of sdio while sclk is high). after every stop condition, the internal address counter is reset. for read operations, the device acknowledge is followed by an eight-bit data word shifted out on falling sclk edges. an internal address counter automatically increments to allow continuous data byte reads, starting with the upper byte of register 0ah, followed by the lower byte of register 0ah, and onward until the lower byte of the last register is reached. the internal address counter then automatically wraps around to the upper byte of register 00h and proceeds from there until continuous reads cease. after each byte of data is read, the controller ic must drive an acknowledge (sdio = 0) if an additional byte of da ta will be requested. data transfer ends with the stop condition. after every stop condition, the internal address counter is reset. for details on timing specific ations and diagrams, refer to table 7, ?2-wire control interface characteristics 1,2,3 ,? on page 9, figure 5, ?2-wire control interface read and write timing parameters,? on page 10 and figure 6, ?2-wire control interface read and write timing diagram,? on page 10. 4.8. reset, powerup, and powerdown driving the rst pin low will disable the si4702-b16 and its control bus interface and reset the registers to their default settings. driving the rst pin high will bring the device out of reset. as the dev ice is brought out of reset, it will sample the state of se veral pins to select between 2-wire and 3-wire control interface operation using one of two busmode selection methods. busmode selection method 1 requires the use of the gpio3, sen , and sdio pins. to use this busmode selection method, the gpio 3 and sdio pins must be sampled low by the device on the rising edge of rst . the user may either drive the gpio3 pin low externally, or leave the pin floating. if the pin is not driven by the user, it will be pulled low by an internal 1 m resistor that is active only while rst is low. the user must drive the sen and sdio pins externally to the proper state. to select 2-wire operation, the sen pin must be sampled high by the device on the rising edge of rst . to select 3-wire operation, the sen pin must be sampled low by the device on the rising edge of rst .
si4702-b16 18 confidential rev. 1.1 refer to table 4, ?reset timing characteristics (busmode select method 1) 1,2,3 ,? on page 6 and figure 1, ?reset timing parameters for busmode select method 1 (gpio3 = 0),? on page 6. busmode selection method 2 requires only the use of the gpio3 and gpio1 pins. this is the recommended busmode selection method when not using the internal crystal oscillator. to us e this busmode selection method, the gpio3 pin must be sampled high on the rising edge of rst . the user must drive the gpio3 pin high externally or pull it up with a resistor of 100 k or less. the user must also drive the gpio1 pin externally to the proper state. to select 2-wire operation, the gpio1 pin must be sampled high by the device on the rising edge of rst . to select 3-wire operation, the gpio1 pin must be sampled low by the device on the rising edge of rst . refer to table 5, ?reset timing characteristics (busmode select method 2) 1,2,3 ,? on page 7 and figure 2, ?reset timing parameters for busmode select method 2 (gpio3 = 1),? on page 7. table 9 summarizes the two bus selection methods. when proper voltages are applied to the si4702-b16, the enable and disable bits in register 02h can be used to select between powerup and powerdown modes. when voltage is first applied to the device, enable = 0 and disable = 0. setting enable = 1 and disable = 0 puts the devi ce in powe rup mode. to power down the device, th e enable and disable bits must both be written to 1. after being written to 1, both bits will be cleared as part of the internal device powerdown sequence. to put the device back into powerup mode, set enable = 1 and disable = 0 as described ab ove. the enable bit should never be written to a 0. 4.9. audio output summation the audio outputs, lout and rout, may be capacitively summed with another device. setting the audio high-z enable (ahizen) bit maintains a dc bias of 0.5 x v io on the lout and rout pins to prevent the esd diodes from clamping to the v io or gnd rail in response to the output swing of the other device. the bias point is set with a 370 k resistor to v io and gnd. register 07h containing the ahizen bit must not be written during the powerup sequence and only takes effect when in powerdown and v io is supplied. in powerup, the lout and rout pins are set to the common-mode voltage specified in table 8, ?fm receiver characteristics 1,2 ,? on page 11, regardless of the state of ahizen. bits 13 :0 of register 07h must be preserved as 0x0100 while in powerdown and as 0x3c04 while in powerup. 4.10. initialization sequence refer to figure 9, ?initializ ation sequence,? on page 19. to initialize the device: 1. supply v a and v d . 2. supply v io while keeping the rst pin low. note that steps 1 and 2 may be reversed. power supplies may be sequenced in any order. 3. select 2-wire or 3-wire control interface bus mode operation as described in section 4.8. "reset, powerup, and powerdown" on page 17. 4. provide rclk. steps 3 and 4 may be reversed when using an external oscillator. wait 500 ms for oscillator startup when using inte rnal oscillator. 5. set the enable bit high and the disable bit low to power up the device. softwa re should wait for the powerup time (as specified by table 8, ?fm receiver characteristics 1,2 ,? on page 11) before continuing with normal part operation. table 9. selecting 2-wire or 3-wire control interface busmode operation 1,2,3 busmode select method sen sdio gpio1 gpio3 2 bus mode 1 0 0 x 0 4 3-wire 1 1 0 x 0 4 2-wire 1 xtal oscillator 0 0 x 0 5 3-wire 1 xtal oscillator 1 0 x 0 5 2-wire 2 x x 0 1 6 3-wire 2 x x 1 1 6 2-wire 2 xtal oscillator na na na na na 2 xtal oscillator na na na na na notes: 1. all parameters are applied on the rising edge of rst . 2. when selecting 2-wire mode, the user must ensure that sclk is high during the rising edge of rst and that it stays high until the first start condition. 3. gpio3 is internally pulled down with a 1 m resistor. 4. gpio3 should be externally driven low, set to high-z (10 m or greater pull-up) or float. 5. gpio3 should be left floating. 6. gpio3 should be externally driven high (100 k or smaller pull-up).
si4702-b16 confidential rev. 1.1 19 to power down the device: 1. (optional) set the ahizen bit high to maintain a dc bias of 0.5 x v io volts at the lout and rout pins while in powerdown mode but preserve the states of the other bits in register 07h. note that in powerup mode, the lout and rout pins are set to the common-mode voltage specified in table 8 on page 11, regardless of the state of ahizen. 2. set the enable bit high and the disable bit high to place the device in powerdown mode. note that all register states are maintained so long as v io is supplied and the rst pin is high. 3. (optional) remove rclk. 4. remove v a and v d supplies as needed. to power up the device (after power down): 1. note that v io is still supplied in this scenario. if v io is not supplied, refer to th e device initialization procedure above. 2. (optional) set the ahizen bit low to disable the dc bias of 0.5 x v io volts at the lout and rout pins, but preserve the states of the other bits in register 07h. note that in powerup, the lout and rout pins are set to the common mode voltage specified in table 8 on page 11, regardless of the state of ahizen. 3. supply v a and v d . 4. provide rclk. wait 500 ms for oscillator startup when using internal oscillator. 5. set the enable bit high and the disable bit low to powerup the device. figure 9. initialization sequence 4.11. programming guide refer to "an230: si4700/01 programming guide" for control interface programming information. va,vd supply rclk pin enable bit 1234 5 rst pin vio supply
si4702-b16 20 confidential rev. 1.1 5. register summary reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00h deviceid pn[3:0] mfgid[11:0] 01h chipid rev[5:0] dev[3:0] firmware[5:0] 02h powercfg dsmute dmute mono 0 0 skmode seekup seek 0 disable 0 0 0 0 0 enable 03h channel tune 0 0 0 0 0 chan[9:0] 04h sysconfig1 0 stcien 0 0 de agcd 0 0 blndadj [1:0] gpio3[1:0] gpio2[1:0] gpio1[1:0] 05h sysconfig2 seekth[7:0] band[1:0] space[1:0] volume[3:0] 06h sysconfig3 smuter[1:0] smutea[1:0] 0 volext sksnr[3:0] skcnt[3:0] 07h test1 xoscen ahizen 08h test2 09h bootconfig 0ah statusrssi 0 stc sf/bl afcrl 0 st rssi[7:0] 0bh readchan readchan[9:0] 0ch reserved 0dh reserved 0eh reserved 0fh reserved note: any register not listed is reserved and shoul d not be written. writing to reserved registers may result in unpredictable behavi or.
si4702-b16 confidential rev. 1.1 21 6. register descriptions reset value = 0x1242 reset value = 0x0850 if enable = 1 reset value = 0x0800 if enable = 0 register 00h. device id bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name pn[3:0] mfgid[11:0] type rr bit name function 15:12 pn[3:0] part number. 0x01 = si4702/03 11:0 mfgid[11:0] manufacturer id. 0x242 register 01h. chip id bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name rev[5:0] dev[3:0] firmware[5:0] type rrr bit name function 15:10 rev[5:0] chip version. 0x02 = rev b 9:6 dev[3:0] device. 0 before powerup. 0001 after powerup = si4702. 1001 after powerup = si4703. 5:0 firmware[5:0] firmware version. 0 before powerup. firmware version after powerup = 10.
si4702-b16 22 confidential rev. 1.1 reset value = 0x0000 register 02h. power configuration bit d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name dsmute dmute mono 0 0 skmode seekup seek 0 disable 00000enable type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name function 15 dsmute softmute disable. 0 = softmute enable (default). 1 = softmute disable. 14 dmute mute disable. 0 = mute enable (default). 1 = mute disable. 13 mono mono select. 0 = stereo (default). 1 = force mono. 12:11 reserved reserved. always write to 0. 10 skmode seek mode. 0 = wrap at the upper or lower band lim it and continue seeking (default). 1 = stop seeking at the upper or lower band limit. 9 seekup seek direction. 0 = seek down (default). 1 = seek up. 8 seek seek. 0 = disable (default). 1=enable. notes: 1. seek begins at the current channel and goes in the direction specified with the seekup bit. seek operation stops when a channel is qualified as valid according to the seek parameters, the entire band has been searched (skmode = 0), or the upper or lower band limit has been reached (skmode = 1). 2. the stc bit is set high when the seek opera tion completes and/or the sf/bl bit is set high if the seek operation was unable to find a channel qualified as valid according to the seek parameters. the stc and sf/bl bits must be set low by setting the seek bit low before the next seek or tune may begin. 3. seek performance for 50 khz channel spacing varies according to rclk tolerance. silicon laboratories recommends 50 ppm rclk crystal tolerance for 50 khz seek performance. 4. a seek operation may be ab orted by setting seek = 0. 7 reserved reserved. always write to 0.
si4702-b16 confidential rev. 1.1 23 reset value = 0x0000 6 disable powerup disable. refer to section 4.8. "reset, powerup, and powerdown" on page 17. default = 0. 5:1 reserved reserved. always write to 0. 0 enable powerup enable. refer to section ?4.8. rese t, powerup, and powerdown?. default = 0. register 03h. channel bit d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name tune 0 0 0 0 0 channel[9:0] type r/w r/w r/w r/w r/w r/w r/w bit name function 15 tune tune. 0 = disable (default). 1=enable. the tune operation begins when the tune bit is set high. the stc bit is set high when the tune operation completes. the stc bit must be set low by setting the tune bit low before the next tune or seek may begin. 14:10 reserved reserved. always write to 0. 9:0 chan[9:0] channel select. channel value for tune operation. if band 05h[7:6] = 00, then freq (mhz) = spacing (mhz) x channel + 87.5 mhz. if band 05h[7:6] = 01, band 05h[7:6] = 10, then freq (mhz) = spacing (mhz) x channel + 76 mhz. chan[9:0] is not updated during a seek operation. readchan[9:0] provides the current tuned channel and is updated during a seek operation and after a seek or tune operation completes. channel spacing is set wit h the bits space 05h[5:4]. bit name function
si4702-b16 24 confidential rev. 1.1 reset value = 0x0000 register 04h. system configuration 1 bit d15 d14 d13d12d11d10d9 d8 d7 d6d5d4d3d2d1d0 name 0 stcien 0 0 de agcd 0 0 blndadj[1:0] gpio3[1:0] gpio2[1:0] gpio1[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name function 15 reserved reserved. always write to 0. 14 stcien seek/tune complete interrupt enable. 0 = disable interrupt (default). 1 = enable interrupt. setting stcien = 1 and gpio2[1:0] = 01 will ge nerate a 5 ms low pulse on gpio2 when the stc 0ah[14] bit is set. 13:12 reserved reserved. always write to 0. 11 de de-emphasis. 0 = 75 s. used in usa (default). 1 = 50 s. used in europe, australia, and japan. 10 agcd agc disable. 0 = agc enable (default). 1 = agc disable. 9:8 reserved reserved. always write to 0. 6:7 blndadj[1:0] stereo/mono blend level adjustment. sets the rssi range for stereo/mono blend. 00 = 31?49 rssi dbv (default). 01 = 37?55 rssi dbv (+6 db). 10 = 19?37 rssi dbv (?12 db). 11 = 25?43 rssi dbv (?6 db). st bit set for rssi values greater than low end of range. 5:4 gpio3[1:0] general purpose i/o 3. 00 = high impedance (default). 01 = mono/stereo indicator (st). the gpio3 will ou tput a logic high when the device is in stereo, otherwise th e device will output a logic low for mono. 10 = low. 11 = high.
si4702-b16 confidential rev. 1.1 25 3:2 gpio2[1:0] general purpose i/o 2. 00 = high impedance (default). 01 = stc interrupt. a logic hi gh will be output unless an in terrupt occurs as described below. 10 = low. 11 = high. setting stcien = 1 will generate a 5 ms lo w pulse on gpio2 when the stc 0ah[14] bit is set. 1:0 gpio1[1:0] general purpose i/o 1. 00 = high impedance (default). 01 = reserved. 10 = low. 11 = high. bit name function
si4702-b16 26 confidential rev. 1.1 reset value = 0x0000 register 05h. system configuration 2 bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name seekth[7:0] band[1:0] space[1:0] volume[3:0] type r/w r/w r/w r/w bit name function 15:8 seekth[7:0] rssi seek threshold. 0x00 = min rssi (default). 0x7f = max rssi. seekth presents the logarithmic rssi threshold for the se ek operation. the si4702 will not validate channels with rssi belo w the seekth value. seekth is one of multiple parameters that can be used to va lidate channels. for more information, see "an284: si4700/0 1 firmware 15 seek ad justability and settings." 7:6 band[1:0] band select. 00 = 87.5?108 mhz (usa,europe) (default). 01 = 76?108 mhz (japan wide band). 10 = 76?90 mhz (japan). 11 = reserved. 5:4 space[1:0] channel spacing. 00 = 200 khz (usa, australia) (default). 01 = 100 khz (europe, japan). 10 = 50 khz. 3:0 volume[3:0] volume. relative value of volume is shifted ?30 dbfs with the volext 06h[8] bit. volext = 0 (default). 0000 = mute (default). 0001 = ?28 dbfs. : : 1110 = ?2 dbfs. 1111 = 0 dbfs. volext = 1. 0000 = mute. 0001 = ?58 dbfs. : : 1110 = ?32 dbfs. 1111 = ?30 dbfs. fs = full scale. volume scale is logarithmic.
si4702-b16 confidential rev. 1.1 27 reset value = 0x0000 register 06h. system configuration 3 bit d15 d14 d13 d12 d11 d10 d9 d8 d7d6d5d4d3d2d1d0 name smuter[1:0] smutea[1:0] 0 0 0 vo lext sksnr[3:0] skcnt[3:0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 15:14 smuter[1:0] softmute attack/recover rate. 00 = fastest (default) 01 = fast 10 = slow 11 = slowest 13:12 smutea[1:0] softmute attenuation. 00 = 16 db (default) 01 = 14 db. 10 = 12 db. 11 = 10 db. 11:9 reserved reserved. always write to zero. 8 volext extended volume range. 0 = disabled (default). 1 = enabled. this bit attenuates the output by 30 db. with the bit set to 0, the 15 volume settings adjust the volume between 0 and ?28 dbfs. with the bit set to 1, the 15 volume set- tings adjust the volume between ?30 and ?58 dbfs. refer to 4.4. "stereo audio processing" on page 15. refer to "an281: si4700/01/02/03 firmware change list." 7:4 sksnr[3:0] seek snr threshold. 0000 = disabled (default). 0001 = min (most stops). 1111 = max (fewest stops). required channel snr for a valid seek channel. 3:0 skcnt[3:0] seek fm impulse detection threshold. 0000 = disabled (default). 0001 = max (most stops). 1111 = min (fewest stops). allowable number of fm impulses for a valid seek channel.
si4702-b16 28 confidential rev. 1.1 reset value = 0x0100 register 07h. test 1 bit d15 d14 d13d12d11d10d9 d8d7d6d5d4d3d2d1d0 name xoscen ahizen reserved type r/w r/w r/w bit name function 15 xoscen crystal oscillator enable. 0 = disable (default). 1=enable. the internal crystal oscillator requires an external 32.768 khz crystal as shown in 2. "typical application schematic" on pa ge 13. the oscillator mu st be enabl ed before powerup (enable = 1) as shown in figure 9, ?initialization sequence,? on page 19. it should only be disabled after powerdown (enable = 0). bits 13:0 of register 07h must be preserved as 0x0100 while in powerdown and as 0x3c04 while in powerup. refer to si4702 internal crystal oscillator errata. 14 ahizen audio high-z enable. 0 = disable (default). 1=enable. setting ahizen maintains a dc bias of 0.5 x v io on the lout and rout pins to pre- vent the esd diodes from clamping to the v io or gnd rail in response to the output swing of another device. regi ster 07h containing the ahizen bit must not be written during the powerup sequence, and high-z on ly takes effect when in powerdown and v io is supplied. bits 13:0 of register 07 h must be preserved as 0x0100 while in pow- erdown and as 0x3c04 while in powerup. 13:0 reserved reserved. if written, these bits should be read first and then written with their pre-existing val- ues. do not write during powerup.
si4702-b16 confidential rev. 1.1 29 reset value = 0x0000 reset value = 0x0000 register 08h. test 2 bit d15d14d13d12d11d10d9 d8d7d6d5d4d3d2d1d0 name reserved type r/w bit name function 15:0 reserved reserved. if written, these bits should be read first and then written with their pre-existing val- ues. do not write during powerup. register 09h. boot configuration bit d15d14d13d12d11d10d9 d8d7d6d5d4d3d2d1d0 name reserved type r/w bit name function 15:0 reserved reserved. if written, these bits should be read first and then written with their pre-existing val- ues. do not write during powerup.
si4702-b16 30 confidential rev. 1.1 reset value = 0x0000 register 0ah. status rssi bit d15d14d13 d12 d11d10d9 d8 d7d6d5d4d3d2d1d0 name 0 stc sf/bl afcrl 0 st rssi[7:0] type rrr r rrrr r bit name function 15 reserved reserved. always write to zero. 14 stc seek/tune complete. 0 = not complete (default). 1 = complete. the seek/tune complete flag is set when t he seek or tune operation completes. setting the seek 02h[8] or tune 03h[15] bit low will clear stc. 13 sf/bl seek fail/band limit. 0 = seek successful. 1 = seek failure/band limit reached. the sf/bl flag is set high when skmode 02h[10] = 0 and the seek operation fails to find a channel qualified as valid according to the seek parameters. the sf/bl flag is set high when skmode 02h[10] = 1 and the upper or lower band limit has been reached. the seek 02h[8] bit must be set low to clear sf/bl. 12 afcrl afc rail. 0 = afc not railed. 1 = afc railed, indicating an invalid channel. audio output is softmuted when set. afcrl is updated after a tune or seek operation completes and indicates a valid or invalid channel. during normal operation, afcrl is updated to reflect changing rf envi- ronments. 11 reserved reserved. always write to zero. 10:9 reserved reserved. if written, these bits should be read first an d then written with their pre-existing values. do not write during powerup. 8st stereo indicator. 0=mono. 1 = stereo. stereo indication is also available on gpio3 by setting gpio3 04h[5:4] = 01. 7:0 rssi[7:0] rssi (received signal strength indicator). rssi is measured units of dbv in 1 db increments with a maximum of approximately 75 dbv. si4702-b16 does not report rssi levels greater than 75 dbuv.
si4702-b16 confidential rev. 1.1 31 reset value = 0x0000 register 0bh. read channel bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name readchan[9:0] type rrrrrr r bit name function 15:10 reserved reserved. if written, these bits should be read first and then written with their pre-existing val- ues. do not write during powerup. 9:0 readchan[9:0] read channel. if band 05h[7:6] = 00, then freq (mhz) = spacing (mhz) x channel + 87.5 mhz. if band 05h[7:6] = 01, band 05h[7:6] = 10, then freq (mhz) = spacing (mhz) x channel + 76 mhz. readchan[9:0] provides the current tuned channel and is updated during a seek operation and after a seek or tune operation completes. spacing and channel are set with the bits, space 05h[5: 4] and chan 03h[9:0].
si4702-b16 32 confidential rev. 1.1 reset value = 0x0000 reset value = 0x0000 register 0ch. reserved bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name type bit name function 15:0 reserved register 0dh. reserved bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name type bit name function 15:0 reserved
si4702-b16 confidential rev. 1.1 33 reset value = 0x0000 reset value = 0x0000 register 0eh. reserved bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name type bit name function 15:0 reserved register 0fh. reserved bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name type bit name function 15:0 reserved
si4702-b16 34 confidential rev. 1.1 7. pin descriptions: si4702-gm pin number(s) name description 1, 20 nc no connect. leave floating. 2 fmip fm rf inputs. 3 rfgnd rf ground. connect to ground plane on pcb. 4, 12, 15, pad gnd ground. connect to ground plane on pcb. 5 rst device reset (act ive low) input. 6 sen serial enable input (active low). 7 sclk serial clock input. 8 sdio serial data input/output. 9 rclk external reference oscillator input. 10 v io i/o supply voltage. 11 v d digital supply voltage. may be connected directly to battery. 13 rout right audio output. 14 lout left audio output. 16 v a analog supply voltage. may be connected directly to battery. 17, 18, 19 gpio3, gpio2, gpio1 general purpose input/output. top view gnd pad 1 gpio1 rclk gnd lout rout rst nc gnd sdio sclk gnd fmip rfgnd gpio2 vd nc gpio3 vio sen va 2 5 4 3 6 15 12 13 14 7 10 9 8 11 17 18 19 20 16
si4702-b16 confidential rev. 1.1 35 8. ordering guide part number* description package type operating temperature SI4702-B16-GM portable broadcast radio tuner fm stereo firmware revision 16 qfn pb-free ?20 to 85 c *note: add an ?(r)? at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
si4702-b16 36 confidential rev. 1.1 9. package markings (top marks) 9.1. si4702 top mark 9.2. top mark explanation mark method: yag laser line 1 marking: part number 02 = si4702 firmware revision 16 = firmware revision 16 line 2 marking: r = die revision b = revision b die ttt = internal code internal tracking code. line 3 marking: circle=0.5mm diameter (bottom-left justified) pin 1 identifier y = year ww = workweek assigned by the assembly house. corresponds to the last sig- nificant digit of the year and workweek of the mold date.
si4702-b16 confidential rev. 1.1 37 10. package outline: si4702-gm figure 10 illustrates the package details for the si4702-gm. table 10 lists t he values for the dimensions shown in the illustration. figure 10. 20-pin quad flat no-lead (qfn) table 10. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.50 0.55 0.60 f 2.53 bsc a1 0.00 0.02 0.05 l 0.35 0.40 0.45 b 0.180.250.30 l1 0.00 ? 0.10 c 0.27 0.32 0.37 aaa ? ? 0.10 d 3.00 bsc bbb ? ? 0.10 d2 1.65 1.70 1.75 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 3.00 bsc eee ? ? 0.10 e2 1.65 1.70 1.75 notes: 1. all dimensions are shown in millimeters unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si4702-b16 38 confidential rev. 1.1 11. pcb land pattern: si4702-gm figure 11 illustrates the pcb land patt ern details for the si4702-gm. table 11 lists the values for the dimensions shown in the illustration. figure 11. pcb land pattern
si4702-b16 confidential rev. 1.1 39 table 11. pcb land pattern dimensions symbol millimeters symbol millimeters min max min max d 2.71 ref ge 2.10 ? d2 1.60 1.80 w ? 0.34 e 0.50 bsc x ? 0.28 e 2.71 ref y 0.61 ref e2 1.60 1.80 ze ? 3.31 f 2.53 bsc zd ? 3.31 gd 2.10 ? notes: general 1. all dimensions shown are in millime ters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes: solder mask design 1. all metal pads are to be non-solder-mask- defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes: stencil design 1. a stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 1.45 x 1.45 mm square aperture should be used for the center pad. this provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component standoff. notes: card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si4702-b16 40 confidential rev. 1.1 12. additional reference resources ? an230: si4700/01/02/03 programming guide ? an231: si4700/01/02/03 head phone and antenna interface ? si4700/01/02/03 evb user?s guide ? an234: si4700/01/02/03 evb test procedure ? an235: si4700/01/02/03 evb quick start guide ? an281: si4700/01/02/03 firmware change list ? an284: si4700 /01/02/03 seek adju stability and settings ? an299: external 32.768 khz crystal oscillator ? si4702/03 internal cr ystal oscillator errata ? si4700/01/02/03 customer support site: http://www.mysilabs.com this site contains all application notes, evaluation b oard schematics and layouts, and evaluation software. nda is required for access. to request access, register at http://www.mysilabs.com and send user?s first and last name, company, nda reference numb er, and mysilabs user name to fminfo@sila bs.com. silicon labs recommends an all-lowercase user name.
si4702-b16 confidential rev. 1.1 41 d ocument c hange l ist revision 0.5 to revision 0.6 ? this data sheet is for re vision b silicon, firmware revision 15. ? added pcb land pattern. revision 0.6 to revision 0.61 ? updated to reflect firmware 15 changes in all text and tables. ? updated table 6, ?3-wire control interface characteristics,? on page 8 with additional timing parameter for t hsen2 . ? updated table 8. "fm receiver characteristics" on page 11. ? updated various texts in ?4 . functional description?. ? updated table 9, ?selecting 2-wire or 3-wire control interface busmode operation 1,2,3 ,? on page 18 to show conditional on rising edge of rst . ? updated ?6. register de scriptions? for clarity. ? added blend level adjustments. ? added volume scale steps. revision 0.61 to revision 0.7 ? updated to reflect firmware 16 changes in all text and tables. ? updated table 8, ?fm rece iver characteristics 1,2 ,? on page 11. ? updated 2. "typical application schematic" on page 13. ? updated 4. "functional description" on page 14. ? updated 5. "register summary" on page 20. ? updated 6. "register descriptions" on page 21. ? updated 9. "package markings (top marks)" on page 36. ? updated 10. "package outline: si4702-gm" on page 37. ? updated 11. "pcb land pattern: si4702-gm" on page 38. ? added additional reference resources to section 12. revision 0.7 to revision 0.71 ? updated "table 8. fm re ceiver characteristics 1,2 " on page 11. revision 0.71 to revision 0.8 ? updated table 3 on page 5. ? updated register 7, ?test 1,? on page 28. ? updated table 8 on page 11. ? updated 4.5. "tuning" on page 15. ? updated 4.8. "reset, powerup, and powerdown" on page 17. revision 0.8 to revision 1.0 ? updated data sheet with si4702-specific information. ? updated table 3 on page 5. ? updated table 8 on page 11. ? updated sections 4, 5, 8, 9, 10, and 11. z removed references to si4703. revision 1.0 to revision 1.1 ? updated table 1, ?recommended operating conditions,? on page 4. ? updated table 3, ?dc characteristics,? on page 5. ? changed table 4 into two separate tables: table 4, ?reset timing characteristics (busmode select method 1) 1,2,3 ,? on page 6 and table 5, ?reset timing characteristics (busmo de select method 2) 1,2,3 ,? on page 7, along with figure 1 and figure 2. ? updated figure 1, ?reset timing parameters for busmode select method 1 (gpio3 = 0),? on page 6. z corrected diagram of t srst1 . ? updated table 7, ?2-wire control interface characteristics 1,2,3 ,? on page 9. z corrected typographical error on tf:out and tf:in, tr:in. z updated table note. ? updated table 8, ?fm receiver characteristics 1,2 ,? on page 11. ? corrected typographical error in 4.5. "tuning" on page 15. ? updated 4.6. "reference clock" on page 16. ? updated 4.7. "control interface" on page 17. ? updated 4.8. "reset, powerup, and powerdown" on page 17. ? updated notes in table 9, ?selecting 2-wire or 3-wire control interface busmode operation 1,2,3 ,? on page 18. ? updated register 1, ?chip id,? on page 21. z corrected typographical error. z corrected reset value information. ? updated register 5, ?system configuration 2,? on page 26. z corrected typographical error. z corrected max rssi seek threshold value for seekth[7:0].
si4702-b16 42 confidential rev. 1.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, texas 78701 tel:1+ (512) 416-8500 fax:1+ (512) 416-9669 toll free:1+ (877) 444-3032 email: fminfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brand names mentioned herein are tradema rks or registered trademarks of their respective holder the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon labo ratories assumes no responsib ility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further not ice. silicon laboratories makes no war- ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon labor atories assume any liability arising out of t he application or use of any produc t or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental da mages. silicon laboratories products are not designed, intended, or authorized for use in applica- tions intended to support or sustain life, or for any other appl ication in which the failure of the silicon laboratories produc t could create a situation where personal injury or death may occur. should bu yer purchase or use silicon laboratories products for any such uni ntended or unauthorized application, buye r shall indemnify and hold sili con laboratories harmless against all claims and damages.

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